Leadless semiconductor package

ABSTRACT

A leadless semiconductor package disposed on a substrate comprises a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a semiconductor package. More particularly,the present invention is related to a leadless semiconductor packagewith an encapsulation formed therein for reducing the thermal mismatchbetween the package and the substrate for carrying said package.

2. Related Art

A well-known semiconductor package, such as a bump chip carrier package(BCC) or a quad flat non-leaded (QFN) package is applicable tocommunication products, portable electronics products, low pin-countspackage structure and packages for high-frequency chips, such as chipwith a working frequency exceeding 12 GHz.

As mentioned above, the bump chip carrier package employs a plurality offlat contacts, for example metal contacts with a size of 0.4 mm*0.3 mm,for electrically connecting the chip and the substrate. Besides, thebump chip carrier package has a chip paddle exposed so as to be attachedto a substrate through solder materials. Thus, the thermal performanceof such BCC package will be enhanced. In addition, the electricalperformance of such a BCC package can be enhanced by employing a groundring.

Referring to FIG. 1, it illustrates a conventional leadlesssemiconductor package or a bump chip carrier package 10. Such package 10mainly comprises a chip 20, a chip paddle or a metal pad 22, a pluralityof leads 24, a plurality of wires 26, a plurality of ground ring 30 andan encapsulation 28. The back surface 21 of the chip 20 is attached tothe chip paddle 22, and the active surface 14 is electrically connectedto the leads 24 or the ground rings 30 through the wires 26. Theencapsulation 28 encapsulates the chip 20, the wires 26, and the groundring 30 and leaves the chip paddle 22 and the leads 24 exposed out ofthe encapsulation 28.

Besides, referring to FIG. 2, the package 10 is attached to a printedcircuit board or a substrate 40 through a solder material 44 by surfacemount technology. However, when there is a lot of difference of thecoefficient of thermal expansion of the encapsulation 28 from that ofthe printed circuits board 40, it is easy to cause thermal stress at thesolder material 44 due to the changes of the working temperature. Thus,the solder material 44 usually bears a lot of cyclic stress so as tocause the fatigue damage and cracks at the solder materials 44. In sucha manner, the package 10 and the printed circuits board 40 will not beable to operate well.

Therefore, providing another leadless semiconductor package to solve thementioned-above disadvantages is the most important task in thisinvention.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, this invention is to provide aleadless semiconductor package having an encapsulation with a lowermodulus so as to prevent the thermal mismatch between the package andthe substrate.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention specifically provides a leadless semiconductor packageapplicable to dispose on a substrate or a printed circuit board, whereinthe leadless semiconductor package mainly comprises a chip, a pluralityof leads, wherein each lead has a metal layer formed on a bottom of saideach lead and a first encapsulation disposed on the metal layer, and asecond encapsulation. Therein, the said each lead is protruded from thesecond encapsulation and electrically connected to the chip. Inaddition, the second encapsulation encapsulates the chip and leaves thechip exposed. However, there is further a chip paddle encapsulated inthe second encapsulation and utilized for carrying the chip.

As mentioned above and to be noted, the modulus of the firstencapsulation is lower than that of the second encapsulation, thethermal mismatch between the package and the substrate will be reducedso as to increase the reliability of such package when the package isattached and mounted to the printed circuit board or substrate.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given herein below illustrations only, and thus are notlimitative of the present invention, and wherein:

FIG. 1 is a cross-sectional view of a conventional leadlesssemiconductor package;

FIG. 2 is a cross-sectional view of a conventional leadlesssemiconductor package attached to a substrate;

FIG. 3 is a cross-sectional view of a leadless semiconductor packageattached to a substrate according to the preferred embodiment of thepresent invention;

FIG. 4 is a cross-sectional view of FIG. 3 specifically showing theleads with the capability of complying with the substrate;

FIG. 5 is a cross-sectional view of a leadless semiconductor packageattached to a substrate according to another preferred embodiment of thepresent invention; and

FIG. 6 is a cross-sectional view of FIG. 5 specifically showing theleads with the capability of complying with the substrate.

DETAILED DESCRIPTION OF THE INVENTION

The leadless semiconductor package according to the preferredembodiments of this invention will be described herein below withreference to the accompanying drawings, wherein the same referencenumbers are used in the drawings and the description to refer to thesame or like parts.

As shown in FIG. 3, it illustrates a first embodiment of this invention.The leadless semiconductor package 100, such as a bump chip carrierpackage or a quad flat non-lead (QFN), is attached to a substrate 140,such as a printed circuit board. Therein, the package 110 mainlycomprises a chip 120, a chip paddle 122, a plurality of leads 124, aplurality of wires 126, a plurality of ground rings 130 and anencapsulation 128. The back surface 112 of the chip 120 is attached tothe chip paddle 122 and the active surface 114 of the chip 120 iselectrically connected to the leads 124 or the ground ring 130.Optionally, the ground ring 130 can be extended to the chip paddle 122.In addition, the leads 124 can be attached to the substrate 140 throughsolder materials 144 by surface mounting technology. To be noted, thedifference of the coefficient of the thermal expansion of theencapsulation from that of the substrate is less than 5 ppm/° C.

As mentioned above, another way to reduce the thermal mismatch betweenthe package 110 and the substrate 140 is to employ an encapsulation witha low modulus, such as silicone with a modulus less than 2 Mpa at thetemperature of 25° C. In such a manner, the encapsulation 128 has lowermodulus, namely, the encapsulation 128 can be easily to shape intoanother shapes. In other words, such package 110 has the capability ofcomplying with the deformation of the substrate 140. Hence, the thermalstress at the solder materials 144 can be reduced so as to prevent thesolder materials 144 from being damaged due to fatigue failure.Consequently, the reliability of solder materials 144 connecting thepackage 110 and the substrate 140 will be increased and improved.

Next, referring to FIG. 5, it illustrates another embodiment. Suchpackage 210 is the same as the first embodiment, attached to a substrate140. The difference of this embodiment from the first embodiment asshown above is that the package 210 mainly has two kinds ofencapsulations formed therein. The first encapsulation 234 is disposedin recesses 232 of a metal panel, with a plated metal layer 124 formedon the recesses 232. Namely, the first encapsulation 234 and the metallayer 124 form the lead. Then, the chip 120 is disposed on the chippaddle 122 of the panel. Next, a transfer molding process is performedto dispose the second encapsulation 236 on the first encapsulation 234and encapsulating the chip 120, the wires 126 and the ground ring 130.Finally, the panel is etched away to leave the metal layers 124 and thechip paddle 122 exposed out of the first encapsulation 234 and thesecond encapsulation 236 respectively. To be noted, each lead isprotruded from the second encapsulation 236. In addition, each lead hasa side wall connecting a bottom and the metal layer 124 is plated on theside wall and the bottom. In such a manner, the metal layer 124 formedon the side wall and the bottom is exposed out of the firstencapsulation 234. Accordingly, when the solder materials 144 connectthe leads and the substrate 140, the side wall and the bottom can beencompassed by the solder materials 144.

As mentioned above, in order to reduce the thermal mismatch of thepackage between the substrate 140, the modulus of the firstencapsulation 234 is lower than 10 Mpa, such as silicone with a modulusless than 2 Mpa at the temperature of 25° C. In such manner, the firstencapsulation 234 has a lower modulus so that the first encapsulation234 can be easily to shape into another shapes. Namely, the package 210is able to comply with the behavior of the substrate 140. Accordingly,referring to FIG. 6, the thermal stress at the solder materials 144 canbe reduced to prevent the solder materials 144 from being damaged due tofatigue failure. Consequently, the reliability of such package 210attached to the substrate 140 will be increased.

Although the invention has been described in considerable detail withreference to certain preferred embodiments, it will be appreciated andunderstood that various changes and modifications may be made withoutdeparting from the spirit and scope of the invention as defined in theappended claims.

1. A leadless semiconductor package, comprising: a plurality of leads,said each lead having a bottom with a metal layer formed thereon and afirst encapsulation disposing on the metal layer; a chip electricallyconnected to the leads; and a second encapsulation encapsulating thechip and disposed on the first encapsulation.
 2. The leadlesssemiconductor package of claim 1, wherein the metal layer are exposedout of the first encapsulation.
 3. The leadless semiconductor package ofclaim 1, further comprising a chip paddle for carrying the chip.
 4. Theleadless semiconductor package of claim 1, wherein the lead is protrudedfrom the second encapsulation.
 5. The leadless semiconductor package ofclaim 3, wherein the chip paddle is exposed out of the secondencapsulation.
 6. The leadless semiconductor package of claim 1, whereinthe chip is grounded to the chip paddle.
 7. The leadless semiconductorpackage of claim 1, wherein the lead further has a side wall connectedto the bottom and the metal layer is disposed on the side wall.
 8. Theleadless semiconductor package of claim 7, wherein the metal layerformed on the side wall is exposed out of the first encapsulation. 9.The leadless semiconductor package of claim 1, wherein the modulus ofthe first encapsulation is less than the modulus of the secondencapsulation.
 10. The leadless semiconductor package of claim 1,wherein the first encapsulation is a silicon resin.
 11. The leadlesssemiconductor package of claim 10, wherein the modulus of the firstencapsulation is less than 2 MPa at the temperature of about 25° C. 12.A leadless semiconductor package, comprising: a plurality of leads, saideach lead having a bottom with a metal layer formed thereon; a chippaddle; a chip disposed on the metal pads and electrically connected tothe leads; an encapsulation encapsulating the chip and disposed on themetal layers; and a substrate attached to the leads.
 13. The leadlesssemiconductor package of claim 12, wherein the difference of thecoefficient of thermal expansion of the substrate from the coefficientof thermal expansion of the encapsulation is about 5 ppm/° C.
 14. Theleadless semiconductor package of claim 12, wherein the chip paddle isattached to the substrate.
 15. The leadless semiconductor package ofclaim 12, further comprising a solder connecting the leads and thesubstrate.
 16. The leadless semiconductor package of claim 15, whereinthe said each lead further comprises a side wall with the metal layerformed thereon and the solder encompasses the side wall and the bottom.17. A leadless semiconductor package, comprising: a plurality of leads,said each lead having a bottom with a metal layer formed thereon; a chipelectrically connected to the leads; and an encapsulation encapsulatingthe chip and disposed on the metal layers, wherein the modulus of theencapsulation is less than 10 Mpa.
 18. The leadless semiconductorpackage of claim 17, wherein the encapsulation is a silicon resin. 19.The leadless semiconductor package of claim 17, wherein the module ofthe encapsulation is less than 2 MPa at the temperature of about 25° C.20. The leadless semiconductor package of claim 17, further comprising achip paddle for carrying the chip.
 21. The leadless semiconductorpackage of claim 18, wherein said each lead is coplanar with the chippaddle.